instruction register
英 [ɪnˈstrʌkʃn ˈredʒɪstə(r)]
美 [ɪnˈstrʌkʃn ˈredʒɪstər]
指令寄存器
双语例句
- Iar-The instruction address register.
iar-指令地址寄存器。 - Its successor was the4040 processor ( released in1974), which had an expanded instruction set, program memory, register set, and stack.
其后面是4040处理器（1974发布），其具有扩展指令集、程序内存、寄存器集和堆栈。 - So this instruction stores the link register ( which holds the return address) into the proper location in the calling function's stack frame.
所以该指令会将链接寄存器（存有返回地址）存储到调用函数堆栈框架的恰当位置。 - The Contractor shall maintain an up to date register of all site instruction forms and shall include such register in the monthly report.
承包商应保留最新的现场指示表登记记录并将其纳入月度报告中。 - Instruction segment descriptor register
指令段描述符寄存器 - The other alternative is to modify the instruction pointer register using the rm command and just type go.
另一个办法是使用rm命令修改指令指针寄存器，然后只要输入go。 - Successfully operate ADDI, ADD, AND and J instruction with correctly register and PC access.
成功运行ADDI，ADD，AND和J指令，寄存器和程序计数器访问正确。 - Control unit ( controller): Control unit is composed of program arithmometer, instruction register and operation controller, ect.
控制器：控制器是由程序计数器、指令寄存器和操作控制器等组成。 - To improve data transmission rate of JTAG interface, instruction register and related control logic are redesigned.
为了提高JTAG接口的数据传输效率，指令寄存器和相关控制逻辑被重新设计。 - The description checks with the photograph instruction segment descriptor register
这一描述与照片相符。指令段描述符寄存器 - Instruction segment descriptor register peripheral command indicator
指令段描述符寄存器外部设备命令指示符 - The collection of instructions is implemented as patterns, each one of which has a different meaning when loading into the instruction register.
指令集合实现为位模式，每个位模式装入测试寄存器时具有不同意义。 - Integration of instruction scheduling and register allocation
指令调度和寄存器分配的集成算法 - Combine Register Allocation with Instruction Scheduling by Register Queue Model
通过寄存器队列模型实现寄存器分配和指令调度 - This thesis attacks two important issues in back end of an optimizing compiler: instruction selection and register allocation.
这篇论文尝试解决优化编译器的后端中的两个重要的问题：指令选择和寄存器分配。 - Then, it puts forward a chain-based IR when considering the demand of data flow analysis, instruction scheduling and register allocation. At last, an algorithm is given.
结合编译器中数据流分析，指令调度和寄存器分配的需求，进一步提出了一种基于链表结构的中间表示及构造算法。 - The key of this design is the design of instructions state machine. Every instruction cycle includes 8 machine clock cycles, is made up of fetch instruction, decoder instruction, execute instruction, writing RAM, writing register and reading RAM etc.
本设计的关键点为指令执行状态级的设计，每个指令周期包括8个机器时钟周期，由取指、译指、执指、RAM读、寄存器写、RAM写等组成； - This article gives a detail discussion on the assembled code optimization from instruction arrangement, register division, condition selection branch and cycle structure based on the core of ARM9TDMI.
本文基于ARM9TDMI内核，从指令调整、寄存器分配、条件分支和循环结构等方面对汇编代码的优化方法进行了详细的论述。 - This paper presents an integrated instruction scheduling and register allocation algorithm for processors with an extended delayed-load architecture.
基于扩展的装入延时体系结构模型，提出了在代码生成过程中针对表达式树的森林的局部寄存器分配和局部指令调度的集成算法。 - The boundary scan adopts the address, data, control register together with instruction register to access relevant space, utilizes original circuit of core of DSP, decreases the cost of hardware;
在边界扫描链设计中，采用了自定义的控制、数据、地址寄存器与指令寄存器相结合的访问ROM和RAM等相应空间方法，与原有的地址译码电路相结合，减少了硬件的开销； - Predicated execution promises to reduce control flow overhead and to enhance optimization, provided that instruction scheduling and register allocation can utilize it efficiently.
许多通用和嵌入式高性能处理器都支持谓词执行，利用谓词执行可以简化程序的控制结构，而且指令调度、寄存器分配也可以利用谓词提高效率。 - This paper mainly introduces the special instructions of PLC such as@ SFTR instruction of reversible register differential and SFTR instruction of reversible register. These instructions can be used to complete the experiment of ordered starting/ stopping three electric motors with load.
介绍PLC专用指令&可逆寄存器微分@SFTR指令及可逆寄存器SFTR指令，完成对3台电动机可逆顺序启动带负载控制的电工技术实验。 - This paper first sets up a computational data flow model, and then explains that a computational data flow graph for the program can be built, using the instruction set of URM ( unlimited register machine) as an example.
首先建立了计算数据流模型，并以无穷存储机器的指令集为例，说明可以为任意程序建立计算数据流图。 - Cooperating Global Instruction Scheduling and Instant Register Allocation
协作式全局指令调度与寄存器分配 - The technology based on instruction set control and register optimization is important to realize the high performance design for micro-control unit and micro-processing unit.
指令集控制和寄存器管理技术是实现高性能控制处理芯片设计的重要技术。 - Present the cooperative instruction scheduling: aim at the phase-ordering problem of instruction scheduling and register allocation.
◆提出协作式指令调度方法：针对寄存器分配与指令调度的时序问题，提出一种协作式指令调度方法。 - Expandable Matrix Computing DSP ( FT-Matrix) has its especial feature of architecture including instruction set and register configure.
可扩展矩阵计算DSP（FT-Matrix）具备其特有的包括指令集格式、寄存器设置等在内的新的体系结构特性。 - But for those processors with connected and partitioned register banks, each bank is in the same word-length and can hold the same value. In such way, operands of an instruction can be placed in multiple register banks.
但在相连寄存器组结构的处理器上，各寄存器组字长相同并有数据通路相连，能存放相同的数据，指令的操作数可来自多个寄存器组。 - Based on the driver of JTAG, a set of functions is provided including data/ instruction register reading/ writing, chain selecting, bypassing and resetting to the caller.
首先在驱动层的基础上实现JTAG操作接口，该接口向调用者提供读写数据、指令寄存器，读取控制器标识，设置扫描链及重启等功能函数。